Magnetic (or magneto-resistive) random access memory (MRAM) circuits have several desirable characteristics such as high speed, high density (i.e., small bit cell size), low power consumption, and no degradation over time, particularly over the dynamic random access memory (DRAM) circuit. MRAM circuits are integrated typically with a complementary metal-oxide semiconductor (CMOS) technology.
FIG. 1A illustrates a section of an exemplary layout for an MRAM circuit 100A, that includes a set of first conducting lines 118 to form word lines and a set of second conducting lines 102 to form bit lines. The set of second conducting lines 102 overlies the set of first conducting lines 118 to define crossover zones 103. Addressable magnetic storage element stacks 122 are disposed within the crossover zones 103. Current drivers 101 are provided for energizing the first conducting lines 118 and the second conducting lines 102. Each of the magnetic storage element stacks 122 correspond to a bit cell in the MRAM circuit 100A, and is isolated from other magnetic storage element stacks 122.
FIG. 16 illustrates a cross sectional view of two adjacent magnetic storage element stacks 122 between the first conducting line 118 and the second conducting line 102, in the region marked ‘X’ in FIG. 1A. In FIG. 16, an access transistor 124 is also shown schematically, corresponding to each of the two magnetic storage element stacks 122, to represent two bit cells A and B. The magnetic storage element stacks 122 are designed to be integrated into a back-end metallization structure following a front-end CMOS processing. In a bit cell, the magnetic storage element stack 122 includes a structure having two ferromagnetic layers which are referred to as a ‘fixed layer’ 110 and a ‘free layer’ 106. The two layers 110,106, are separated by a non-magnetic barrier layer that is referred to as ‘a tunnel oxide layer’ 108. All the three layers along with an extended bottom electrode 112 are arranged to form a magnetic tunnel junction (MTJ) stack 122. The free layer 106 is connected to an upper metallization layer through an upper interface via hole 104. The bottom electrode 112 is connected to a lower metallization layer, through a lower interface via hole 116. The upper metallization layer is patterned to include the bit lines corresponding to each MTJ stack 122. The lower metallization layer is patterned to include a write word line 118c and a read word line 118b, for reading and writing operations from and into each MTJ stack 122. A connection 118a between the lower metallization layer and a corresponding access transistor 124 for the reading operation in a bit cell, is also shown. The write word line 118c for the writing operation in a bit cell has no contact with the bottom electrode 112, and when energized, induces a magnetic field at a junction of the MTJ stack 122. The upper and lower metallization layers are shown to be an M3 layer and an M2 layer respectively. For fabricating this structure with the MTJ stack 122, after patterning the M2 layer and before forming the M3 layer, four masking and etching steps are likely to be required, such as: a) lower interface via mask and etch for defining the lower interface via hole 116, in order to connect the individual bottom electrodes 112 to the lower metallization layer, b) bottom electrode mask and etch for defining the individual bottom electrodes 112, c) magnetic stack etch mask and etch for defining the individual MTJ stacks 122 up to the bottom electrode 112, and d) upper interface via mask and etch for defining the upper interface via hole 104, in order to connect the free layers 106 to the upper metallization layer. The fully isolated individual magnetic storage element stacks 122 are encapsulated by dielectric regions 120. Smaller the area of the MTJ stack 122, better is the efficiency of the writing operation. For each of the bit cells A and B, the bottom electrode 112 extends beyond the area of the free layer 106, the tunnel oxide layer 108 and the fixed layer 110, and accommodates the corresponding write word line 118c and the corresponding read lines 118a,b. 